As I promised, in an earlier lesson, I am going to go through an in-depth explaination of ALL the 8085 instructions.
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Intel
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88888
000
88888 5555555 A |
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8 8 0 0
8 8 5 A
A |
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8 8 0 0 0
8 8 5 A A |
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88888 0 0
0 88888 555555 AAAAAAA |
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8 8 0 0 0
8 8 5 A A |
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8 8 0 0
8 8
5 A A |
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88888
000
88888
555555 A A |
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8085A MICROPROCESSOR Instruction Set Summary |
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_________
_________
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_| \__/
|_
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| --> X1
|_|1 40|_|
Vcc (+5V)
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_|
|_
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| --> X2
|_|2
39|_| HOLD <-- |
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_|
|_
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| <-- RESET OUT |_|3 38|_|
HLDA --> |
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_|
|_
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<-- SOD |_|4
37|_| CLK (OUT) -->
|
|
_|
|_ ________ |
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--> SID |_|5
36|_| RESET IN <--
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_|
|_
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--> TRAP |_|6
35|_| READY <-- |
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_|
|_ _
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| --> RST 7.5
|_|7
34|_| IO/M --> |
|
_|
|_
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| --> RST 6.5
|_|8
33|_| S1 --> |
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_|
|_ __
|
| --> RST 5.5
|_|9
32|_| RD --> |
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_|
|_ __
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--> INTR |_|10 8085A 31|_| WR --> |
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____ _|
|_
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| <-- INTA |_|11
30|_| ALE --> |
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_|
|_
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<--> AD0 |_|12
29|_| S0 --> |
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_|
|_
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<--> AD1 |_|13
28|_| A15 --> |
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_|
|_
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<--> AD2 |_|14
27|_| A14 --> |
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_|
|_
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<--> AD3 |_|15
26|_| A13 --> |
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_|
|_
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<--> AD4 |_|16
25|_| A12 --> |
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_|
|_ |
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<--> AD5 |_|17
24|_| A11 --> |
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_|
|_
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<--> AD6 |_|18
23|_| A10 --> |
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_|
|_ |
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<--> AD7 |_|19
22|_| A9 --> |
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_|
|_
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| (Gnd) Vss
|_|20
21|_| A8 --> |
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|______________________|
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Copyright (C) J.P.Bowen 1985|
Instructions can be categorized according
to their method of addressing the hardware registers and/or memory.
Implied Addressing:
The addressing mode of certain
instructions is implied by the instruction’s function. For example, the STC
(set carry flag) instruction deals only with the carry flag, the DAA (decimal
adjust accumulator) instruction deals with the accumulator.
Register Addressing:
Quite a large set of instructions call for
register addressing. With these instructions, you must specify one of the
registers A through E, H or L as well as the operation code. With these
instructions, the accumulator is implied as a second operand. For example, the
instruction CMP E may be interpreted as 'compare the contents of the E register
with the contents of the accumulator.
Most of the instructions that use register
addressing deal with
8-bit values. However, a few of these
instructions deal with 16-bit register pairs. For example, the PCHL instruction exchanges the contents of
the program counter with the contents of the H and L registers.
Immediate Addressing:
Instructions that use immediate addressing
have data assembled as a part of the instruction itself. For example, the
instruction CPI 'C' may be interpreted as ‘compare the contents of the
accumulator with the letter C. When assembled, this instruction has the
hexadecimal value FE43. Hexadecimal 43 is the internal representation for the
letter C. When this instruction is executed, the processor fetches the first
instruction byte and determines that it must fetch one more byte. The processor
fetches the next byte into one of its internal registers and then performs the
compare operation.
Notice that the names of the immediate
instructions indicate that they use immediate data. Thus, the name of an add
instruction is ADD; the name of an add immediate instruction is ADI.
All but two of the immediate instructions
uses the accumulator as an implied operand, as in the CPI instruction shown
previously. The MVI (move immediate) instruction can move its immediate data to
any of the working registers including the accumulator or to memory. Thus, the
instruction MVI D, OFFH moves the hexadecimal
value FF to the D register.
The LXI instruction (load register pair
immediate) is even more unusual in that its immediate data is a 16-bit value.
This instruction is commonly used to load addresses into a register pair. As
mentioned previously, your program must initialize the stack pointer; LXI is
the instruction most commonly used for this purpose. For example, the
instruction LXI SP,3OFFH loads the stack pointer with the hexadecimal value
30FF.
Direct Addressing:
Jump instructions include a 16-bit address
as part of the instruction. For example, the instruction JMP 1000H causes a
jump to the hexadecimal address 1000 by replacing the current contents of the
program counter with the new value 1000H.
Instructions that include a direct address require three
bytes of storage: one for the instruction code, and two for the 16-bit address
Register
Indirect Addressing:
Register indirect instructions reference memory via a
register pair. Thus, the instruction MOV M,C moves the contents of the C
register into the memory address stored in the H and L register pair. The
instruction LDAX B loads the accumulator with the byte of data specified by the
address in the B and C
register pair.
Combined
Addressing Modes:
Some instructions use a combination of addressing modes. A
CALL instruction, for example, combines direct addressing and register indirect
addressing. The direct address in a CALL instruction specifies the address of
the desired subroutine; the register indirect address is the stack pointer. The
CALL instruction pushes the current contents of the program counter into the
memory location specified by the stack pointer.
Timing
Effects of Addressing Modes:
Addressing modes affect both the amount of time required for
executing an instruction and the amount of memory required for its storage. For
example, instructions that use implied or register addressing, execute very
quickly since they deal directly with the processor’s hardware or with data
already present in hardware registers. Most important, however is that the
entire instruction can be fetched with a single memory access. The number of
memory accesses required is the single greatest factor in determining execution
timing. More memory accesses therefore require more execution time. A CALL
instruction for example, requires five memory accesses: three to access the
entire instruction and two more to push the contents of the program counter
onto the stack.
The processor can access memory once during each processor
cycle. Each cycle comprises a variable number of states. (See below and the appendix
of “USING THE SDK-85 MICROPROCESSOR TRAINER”). The length of a state depends on
the clock frequency specified for your system, and may range from 480
nanoseconds to 2 microseconds. Thus, the timing for a four state instruction
may range from 1.920 microseconds through 8 microseconds. (The 8085 have a maximum
clock frequency of 5 MHz and therefore a minimum state length of 200
nanoseconds.)
Instruction
Naming Conventions:
The mnemonics assigned to the instructions are designed to
indicate the function of the instruction. The instructions fall into the
following functional categories:
Data
Transfer Croup:
The data transfer instructions move data between registers
or between memory and registers.
MOV Move
MVI Move
Immediate
LDA Load
Accumulator Directly from Memory
STA Store
Accumulator Directly in Memory
LHLD Load
H & L Registers Directly from Memory
SHLD Store
H & L Registers Directly in Memory
An 'X' in the name of a data transfer instruction implies that it deals with
a register pair (16-bits);
LXI Load Register Pair with Immediate
data
LDAX Load
Accumulator from Address in Register Pair
STAX Store
Accumulator in Address in Register Pair
XCHG Exchange
H & L with D & E
XTHL Exchange
Top of Stack with H & L
Arithmetic
Group:
The arithmetic instructions add, subtract,
increment, or decrement data in
registers or memory.
ADD Add
to Accumulator
ADI Add
Immediate Data to Accumulator
ADC Add
to Accumulator Using Carry Flag
ACI Add
Immediate data to Accumulator Using Carry
SUB Subtract
from Accumulator
SUI Subtract
Immediate Data from Accumulator
SBB Subtract
from Accumulator Using Borrow (Carry) Flag
SBI Subtract
Immediate from Accumulator Using Borrow (Carry) Flag
INR Increment
Specified Byte by One
DCR Decrement
Specified Byte by One
INX Increment
Register Pair by One
DCX Decrement Register Pair by One
DAD Double
Register Add; Add Content of Register
Pair
to H & L Register Pair
Logical
Group:
This group performs logical (Boolean)
operations on data in registers and memory and on condition flags.
The logical AND, OR, and Exclusive OR
instructions enable you to set specific bits in the accumulator ON or OFF.
ANA Logical
AND with Accumulator
ANI Logical
AND with Accumulator Using Immediate Data
ORA Logical
OR with Accumulator
OR Logical
OR with Accumulator Using Immediate Data
XRA Exclusive
Logical OR with Accumulator
XRI Exclusive
OR Using Immediate Data
The Compare instructions compare the
content of an 8-bit value with the contents of the accumulator;
CMP Compare
CPI Compare
Using Immediate Data
The rotate instructions shift the
contents of the accumulator one bit position to the left or right:
RLC Rotate
Accumulator Left
RRC Rotate
Accumulator Right
RAL Rotate
Left Through Carry
RAR Rotate
Right Through Carry
Complement and carry flag instructions:
CMA Complement
Accumulator
CMC Complement
Carry Flag
STC Set
Carry Flag
Branch Group:
The branching instructions alter normal
sequential program flow, either unconditionally or conditionally. The
unconditional branching instructions are as follows:
JMP Jump
CALL Call
RET Return
Conditional branching instructions
examine the status of one of four condition flags to determine whether the
specified branch is to be executed. The conditions that may be specified are as
follows:
NZ Not
Zero (Z = 0)
Z Zero
(Z = 1)
NC No
Carry (C = 0)
C Carry
(C = 1)
PO Parity
Odd (P = 0)
PE Parity
Even (P =
1)
P Plus
(S = 0)
M Minus
(S = 1)
Thus, the conditional branching
instructions are specified as follows:
Jumps Calls Returns
C CC RC (Carry)
INC CNC RNC (No Carry)
JZ CZ RZ (Zero)
JNZ CNZ RNZ (Not Zero)
JP CP RP (Plus)
JM CM RM (Minus)
JPE CPE RPE (Parity Even)
JP0 CPO RPO (Parity Odd)
Two other instructions can affect a
branch by replacing the contents or
the program counter:
PCHL Move
H & L to Program Counter
RST Special
Restart Instruction Used
with
Interrupts
Stack I/O,
and Machine Control Instructions:
The following instructions affect the
Stack and/or Stack Pointer:
PUSH Push
Two bytes of Data onto the Stack
POP Pop
Two Bytes of Data off the Stack
XTHL Exchange
Top of Stack with H & L
SPHL Move
content of H & L to Stack Pointer
The I/0 instructions are as follows:
IN Initiate
Input Operation
OUT Initiate
Output Operation
The Machine Control instructions are as
follows:
EI Enable
Interrupt System
DI Disable
Interrupt System
HLT Halt
NOP No
Operation
----------------------------------------------------------------
|Mnemonic
|Op|SZAPC|~s|Description
|Notes |
|---------+--+-----+--+--------------------------+-------------|
|ACI
n |CE|*****| 7|Add
with Carry Immediate
|A=A+n+CY
|
|ADC
r |8F|*****| 4|Add
with Carry
|A=A+r+CY(21X)|
|ADC
M |8E|*****| 7|Add
with Carry to Memory
|A=A+[HL]+CY |
|ADD
r |87|*****|
4|Add |A=A+r (20X)|
|ADD
M |86|*****| 7|Add to
Memory
|A=A+[HL]
|
|ADI
n |C6|*****| 7|Add
Immediate
|A=A+n
|
|ANA
r |A7|****0| 4|AND
Accumulator
|A=A&r (24X)|
|ANA
M |A6|****0| 7|AND
Accumulator and Memory|A=A&[HL] |
|ANI
n |E6|**0*0| 7|AND
Immediate
|A=A&n
|
|CALL
a |CD|-----|18|Call
unconditional |-[SP]=PC,PC=a|
|CC
a |DC|-----|
9|Call on Carry
|If CY=1(18~s)|
|CM
a |FC|-----|
9|Call on Minus
|If S=1 (18~s)|
|CMA |2F|-----|
4|Complement Accumulator
|A=~A |
|CMC |3F|----*|
4|Complement Carry |CY=~CY |
|CMP
r |BF|*****|
4|Compare
|A-r
(27X)|
|CMP
M |BF|*****| 7|Compare
with Memory
|A-[HL] |
|CNC
a |D4|-----| 9|Call on
No Carry |If
CY=0(18~s)|
|CNZ
a |C4|-----| 9|Call on
No Zero |If
Z=0 (18~s)|
|CP
a |F4|-----|
9|Call on Plus
|If S=0 (18~s)|
|CPE
a |EC|-----| 9|Call on
Parity Even
|If P=1 (18~s)|
|CPI
n |FE|*****| 7|Compare
Immediate |A-n
|
|CPO
a |E4|-----| 9|Call on
Parity Odd |If P=0 (18~s)|
|CZ
a |CC|-----|
9|Call on Zero
|If Z=1 (18~s)|
|DAA |27|*****| 4|Decimal Adjust
Accumulator|A=BCD format |
|DAD
B |09|----*|10|Double
Add BC to HL |HL=HL+BC |
|DAD
D |19|----*|10|Double
Add DE to HL |HL=HL+DE |
|DAD
H |29|----*|10|Double
Add HL to HL |HL=HL+HL |
|DAD
SP |39|----*|10|Double Add
SP to HL
|HL=HL+SP
|
|DCR
r |3D|****-|
4|Decrement
|r=r-1 (0X5)|
|DCR
M
|35|****-|10|Decrement Memory
|[HL]=[HL]-1 |
|DCX
B |0B|-----|
6|Decrement BC
|BC=BC-1
|
|DCX
D |1B|-----|
6|Decrement DE
|DE=DE-1
|
|DCX
H |2B|-----|
6|Decrement HL
|HL=HL-1
|
|DCX
SP |3B|-----| 6|Decrement
Stack Pointer |SP=SP-1 |
|DI
|F3|-----| 4|Disable Interrupts |
|
|EI
|FB|-----| 4|Enable Interrupts |
|
|HLT |76|-----|
5|Halt
|
|
|IN
p
|DB|-----|10|Input
|A=[p] |
|INR
r |3C|****-|
4|Increment
|r=r+1 (0X4)|
|INR
M
|3C|****-|10|Increment Memory
|[HL]=[HL]+1 |
|INX
B |03|-----|
6|Increment BC
|BC=BC+1
|
|INX
D |13|-----|
6|Increment DE
|DE=DE+1
|
|INX
H |23|-----|
6|Increment HL
|HL=HL+1
|
|INX
SP |33|-----| 6|Increment
Stack Pointer |SP=SP+1 |
|JMP
a |C3|-----| 7|Jump
unconditional |PC=a
|
|JC
a |DA|-----|
7|Jump on Carry
|If CY=1(10~s)|
|JM
a |FA|-----|
7|Jump on Minus |If S=1 (10~s)|
|JNC
a |D2|-----| 7|Jump on
No Carry |If
CY=0(10~s)|
|JNZ
a |C2|-----| 7|Jump on
No Zero |If
Z=0 (10~s)|
|JP
a |F2|-----|
7|Jump on Plus
|If S=0 (10~s)|
|JPE
a |EA|-----| 7|Jump on
Parity Even |If P=1 (10~s)|
|JPO
a |E2|-----| 7|Jump on
Parity Odd |If P=0 (10~s)|
|JZ
a |CA|-----|
7|Jump on Zero
|If Z=1 (10~s)|
|LDA
a |3A|-----|13|Load
Accumulator direct
|A=[a] |
|LDAX
B |0A|-----| 7|Load
Accumulator indirect |A=[BC] |
|LDAX
D |1A|-----| 7|Load
Accumulator indirect |A=[DE] |
|LHLD
a |2A|-----|16|Load HL
Direct
|HL=[a]
|
|LXI
B,nn |01|-----|10|Load Immediate BC |BC=nn |
|LXI
D,nn |11|-----|10|Load Immediate DE |DE=nn |
|LXI
H,nn |21|-----|10|Load Immediate HL |HL=nn |
|LXI
SP,nn|31|-----|10|Load Immediate Stack Ptr |SP=nn |
|MOV
r1,r2|7F|-----| 4|Move register to register |r1=r2 (1XX)|
|MOV
M,r |77|-----| 7|Move register to
Memory |[HL]=r (16X)|
|MOV
r,M |7E|-----| 7|Move Memory to
register |r=[HL] (1X6)|
|MVI
r,n |3E|-----| 7|Move
Immediate
|r=n
(0X6)|
|MVI
M,n |36|-----|10|Move Immediate to
Memory |[HL]=n |
|NOP |00|-----| 4|No
Operation
|
|
|ORA
r |B7|**0*0|
4|Inclusive OR Accumulator
|A=Avr (26X)|
|ORA
M |B6|**0*0|
7|Inclusive OR Accumulator
|A=Av[HL]
|
|ORI
n |F6|**0*0|
7|Inclusive OR Immediate
|A=Avn |
|OUT
p |D3|-----|10|Output
|[p]=A |
|PCHL |E9|-----| 6|Jump HL
indirect
|PC=[HL]
|
|POP
B |C1|-----|10|Pop
BC
|BC=[SP]+
|
|POP
D |D1|-----|10|Pop
DE
|DE=[SP]+
|
|POP
H |E1|-----|10|Pop
HL
|HL=[SP]+
|
|POP
PSW |F1|-----|10|Pop Processor
Status Word |{PSW,A}=[SP]+|
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic
|Op|SZAPC|~s|Description
|Notes |
|---------+--+-----+--+--------------------------+-------------|
|PUSH
B |C5|-----|12|Push BC
|-[SP]=BC
|
|PUSH
D |D5|-----|12|Push DE
|-[SP]=DE
|
|PUSH
H |E5|-----|12|Push HL
|-[SP]=HL
|
|PUSH
PSW |F5|-----|12|Push Processor Status Word|-[SP]={PSW,A}|
|RAL |17|----*|
4|Rotate Accumulator Left
|A={CY,A}<- |
|RAR |1F|----*|
4|Rotate Accumulator Righ
|A=->{CY,A} |
|RET
|C9|-----|10|Return
|PC=[SP]+
|
|RC
|D8|-----| 6|Return on Carry |If
CY=1(12~s)|
|RIM |20|-----|
4|Read Interrupt Mask |A=mask |
|RM
|F8|-----| 6|Return on Minus |If
S=1 (12~s)|
|RNC |D0|-----|
6|Return on No Carry |If CY=0(12~s)|
|RNZ |C0|-----|
6|Return on No Zero |If Z=0 (12~s)|
|RP
|F0|-----| 6|Return on Plus
|If S=0 (12~s)|
|RPE |E8|-----|
6|Return on Parity Even
|If P=1 (12~s)|
|RPO |E0|-----|
6|Return on Parity Odd |If P=0 (12~s)|
|RZ
|C8|-----| 6|Return on Zero
|If Z=1 (12~s)|
|RLC |07|----*|
4|Rotate Left Circular |A=A<- |
|RRC |0F|----*|
4|Rotate Right Circular
|A=->A |
|RST
z
|C7|-----|12|Restart
(3X7)|-[SP]=PC,PC=z|
|SBB
r |9F|*****|
4|Subtract with Borrow |A=A-r-CY |
|SBB
M |9E|*****|
7|Subtract with Borrow |A=A-[HL]-CY |
|SBI
n |DE|*****|
7|Subtract with Borrow Immed|A=A-n-CY |
|SHLD
a |22|-----|16|Store HL
Direct
|[a]=HL
|
|SIM |30|-----|
4|Set Interrupt Mask |mask=A |
|SPHL |F9|-----| 6|Move HL
to SP
|SP=HL
|
|STA
a |32|-----|13|Store
Accumulator |[a]=A |
|STAX
B |02|-----| 7|Store
Accumulator indirect|[BC]=A |
|STAX
D |12|-----| 7|Store
Accumulator indirect|[DE]=A |
|STC |37|----1|
4|Set Carry
|CY=1 |
|SUB
r |97|*****|
4|Subtract |A=A-r (22X)|
|SUB
M |96|*****|
7|Subtract Memory
|A=A-[HL]
|
|SUI
n |D6|*****|
7|Subtract Immediate |A=A-n |
|XCHG |EB|-----| 4|Exchange
HL with DE
|HL<->DE |
|XRA
r |AF|**0*0|
4|Exclusive OR Accumulator
|A=Axr (25X)|
|XRA
M |AE|**0*0|
7|Exclusive OR Accumulator
|A=Ax[HL]
|
|XRI
n |EE|**0*0|
7|Exclusive OR Immediate
|A=Axn |
|XTHL |E3|-----|16|Exchange
stack Top with HL|[SP]<->HL |
|------------+-----+--+----------------------------------------|
|
PSW
|-*01 | |Flag
unaffected/affected/reset/set |
|
S |S | |Sign (Bit 7)
|
|
Z | Z | |Zero (Bit 6)
|
|
AC | A
| |Auxilary Carry (Bit
4)
|
|
P | P | |Parity (Bit 2)
|
|
CY | C| |Carry (Bit 0)
|
|---------------------+----------------------------------------|
| a
p
|Direct addressing
|
| M
z
|Register indirect addressing
|
| n
nn
|Immediate addressing
|
|
r
|Register addressing
|
|---------------------+----------------------------------------|
|DB
n(,n)
|Define Byte(s)
|
|DB
'string' |Define Byte
ASCII character string |
|DS
nn
|Define Storage Block
|
|DW
nn(,nn) |Define Word(s)
|
|---------------------+----------------------------------------|
|
A B C D E
H L |Registers (8-bit)
|
|
BC DE HL |Register
pairs (16-bit)
|
|
PC |Program
Counter register (16-bit) |
|
PSW
|Processor Status Word (8-bit) |
|
SP
|Stack Pointer register (16-bit) |
|---------------------+----------------------------------------|
|
a nn
|16-bit address/data (0 to 65535) |
|
n p
|8-bit data/port (0 to 255)
|
|
r
|Register (X=B,C,D,E,H,L,M,A)
|
|
z
|Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)|
|---------------------+----------------------------------------|
|
+ -
|Arithmetic addition/subtraction
|
|
& ~
|Logical AND/NOT
|
|
v x
|Logical inclusive/exclusive OR
|
|
<- ->
|Rotate left/right
|
|
<->
|Exchange
|
| [
]
|Indirect addressing
|
| [
]+ -[ ] |Indirect
address auto-inc/decrement |
| {
}
|Combination operands
|
| ( X
)
|Octal op code where X is a 3-bit code |
| If (
~s)
|Number of cycles if condition true |
----------------------------------------------------------------